In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there have been, and continue to be, efforts toward scaling down device dimensions (e.g., at sub-micron levels) on semiconductor wafers. In order to accomplish such high device packing densities, smaller and smaller features sizes are required. This may include the width and spacing of interconnecting lines, spacing and diameter of contact holes, and the surface geometry, such as corners and edges, of various features. The dimensions of and between such small features can be referred to as critical dimensions (CDs). Reducing CDs, and reproducing more accurate CDs facilitates achieving such higher device densities. Conventional etch processes have either lacked feedback control systems, requiring pre-calculated etching steps, or have had indirect feedback control, which is based on indirect information (e.g., amount of gas generated by plasma gas discharge etching) or have required sacrificing valuable wafer space. Such pre-determined calculations and/or indirect feedback control do not provide adequate monitoring and thus do not facilitate precise control over the etch process. Another conventional form of etch control is performed by reproducing etch times. But such time based control does not account for wafer to wafer variations and does not account for wafers with various feature densities. Monitoring tools employed in conjunction with metrology based feed-forward information are known in the art and provide improvements over time based control. But such metrology feed-forward systems can be improved by more accurate monitoring, better CD recognition and more precise feed-forward information.
The process of manufacturing semiconductors, or integrated circuits (commonly called ICs, or chips), typically consists of more than a hundred steps, during which hundreds of copies of an integrated circuit may be formed on a single wafer. Each step can affect the CDs of the ICs. Generally, the manufacturing process involves creating several patterned layers on and into the substrate that ultimately forms the complete integrated circuit. This layering process creates electrically active regions in and on the semiconductor wafer surface. The size, shape and isolation of such electrically active regions, and thus the reliability and performance of integrated circuits employing such regions thus depend, at least in part, on the precision with which etching can be performed.
Unfortunately, commonly used fabrication systems check devices for CDs near or at the end of fabrication, or at pre-scheduled time intervals. These types of endpoint and interval detection methods can be problematic for several reasons. For example, at late stages in the fabrication process, the presence of at least one malformed portion of a device may render the whole semiconductor device unusable, forcing it to be discarded. In addition, post-fabrication detection/quality control data do not provide a user with real-time information related to the device being fabricated. Post-fabrication data may only allow an estimation or a projection as to what adjustments are needed to correct the fabrication errors and/or flaws. Such estimations and/or projections concerning necessary adjustments may lead to continued or recurring fabrication errors. Moreover, such a lengthy adjustment process may cause subsequent fabricated wafers to be wasted in the hopes of mitigating etch process errors.
Visual inspection methods have been important in both production and development of integrated circuits. Visually inspecting developed photoresist patterns from a dose-focus matrix is well-known in the art. While visual inspection techniques may be simple to implement, they are difficult to automate. Further, visual techniques employing scanning electron microscopes (SEM) and atomic force microscopes (AFM) can be expensive, time-consuming and/or destructive.
Due to the extremely fine patterns that are exposed on the photo resist, controlling the etching process, whereby oxide and/or other conductive or insulating layers are removed, is a significant factor in achieving desired critical dimensions. Achieving greater precision in etch processes can result, for example, in achieving more precise CDs (e.g., desired lengths and widths between layers, between features and within features). Thus, an efficient system, and/or method, to monitor and control etch processes is desired to facilitate manufacturing ICs exhibiting desired critical dimensions.